1. Field of the Invention
The present invention relates to a semiconductor device which operates at a low source voltage by dynamically varying its threshold voltage.
2. Description of the Related Art
In these years, wide use is being made of personal digital assistant devices, a representative of which is a mobile telephone. Since such a mobile device is generally driven with a battery, a device of lower power consumption is strongly desired.
In order to realize lower power consumption without sacrificing a high-speed operation it is necessary to maintain the driving power by increasing the drain saturation current as well as to lower the source voltage by lowering the threshold voltage.
As a device solving such a problem, there has been proposed a DTMOS (Dynamic Threshold Voltage MOSFET) which exhibits reduced leakage current while having a high driving ability even at a low voltage (see F. Assaderaghi et. al.,) “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation P. 510-512”. The DTMOS has the characteristic that the gate electrode and the body region are electrically connected to each other. When a voltage is applied to the gate in a state thus short-circuited with the body, a forward bias voltage having a magnitude equal to that of the gate voltage is applied to the substrate active region. Thus, the DTMOS assumes the same state as an ordinary transistor when the gate is off, whereas when the gate is on, the threshold lowers because the substrate is increasingly biased forwardly with increasing voltage applied to the gate. This effect causes an effective applied gate voltage to increase, which produces a gate overdrive effect thereby realizing high driving power.
A problem arising in the fabrication of such a DTMOS is involved in methods of interconnecting the gate electrode and the body region.
FIG. 17 is a plan view schematically illustrating a connecting structure between the gate electrode and the body region in a conventional DTMOS; FIG. 18 is a sectional view taken along line XVIII—XVIII of FIG. 17; FIG. 19 is a sectional view taken along line XIX—XIX of FIG. 17; and FIG. 20 is a sectional view taken along line XX—XX of FIG. 17.
In the DTMOS (of n-channel type) shown in FIGS. 17 to 20, a gate insulator 3 is formed over a device active region 110 of a semiconductor substrate (hereinafter referred to as “substrate”) 1 and a gate electrode G is formed on the gate insulator 3. Source/drain regions 2 of n-type are formed in respective of regions situated directly under the surface of the substrate 1 on both sides of the gate electrode G in plan view. An interlayer dielectric 5 is formed to cover the gate electrode G and the gate insulator 3. The substrate 1 is doped into p-type. A high p-type impurity concentration region (hereinafter referred to as “p+ region”) 4 is formed in a region situated directly under the surface of the substrate 1 and beneath a widthwise end of the gate electrode G in plan view. A first contact hole H1 is formed to extend through the gate insulator 3 and the interlayer dielectric 5 so as to interconnect the p+ region and the widthwise end of the gate electrode G. The first contact hole H1 is filled up with an electric conductor to form a first contact C1. Thus, the gate electrode G is electrically connected to a region 103 of the device active region 110 exclusive of the source/drain regions 2,2. (Accordingly, the region 103 includes the p+ region. The region 103 will hereinafter be referred to as “body region”.) Reference characters H2 and C2 denote a second contact hole and a second contact, respectively, which interconnect the source/drain regions 2 and non-illustrated aluminum wire. In the present specification the direction along the channel length (the direction along the length of the gate electrode) is referred to as “X direction” while the direction along the channel width (the direction along the width of the gate electrode) referred to as “Y direction”.
This structure has the characteristic that it is possible to implement the structure without changing the process and, in addition, to suppress an increase in the device area because the structure has the sole first contact C1.
However, the connecting structure between the gate electrode G and the body region 103 utilizing the sole single first contact C1 involves a problem that variation in contact resistance occurs since the contact area varies because of positional deviation and dimensional deviation between the gate electrode G and the first contact C1.
The contact resistance is a very important parameter determining a CR delay component in analog circuits. Variation in contact resistance not only results in variation in device characteristics but also cause interference with circuit designing. For this reason, such variation in contact resistance need be reduced to the limit.
FIGS. 21A and 21B and FIGS. 22A and 22B are plan views illustrating positional relations between the gate electrode and the first contact in the conventional DTMOS; specifically, FIGS. 21A and 21B illustrate the cases where the position of the first contact deviates in the X direction, while FIGS. 22A and 22B illustrate the cases where the position of the first contact deviates in the Y direction.
As shown in FIGS. 17 and 20, the first contact hole H1 is formed to extend over the gate electrode G and the p+ region 4 in plan view. In FIG. 20 reference character 51 depicts a contact portion between the first contact C1 and the gate electrode G and reference character 52 depicts a contact portion between the first contact C1 and the p+ region 4 (hence the body region 103). As apparent from FIGS. 21A and 21B, when the first contact C1 deviates in the X direction, the area of the contact portions of the first contact C1 in contact with the gate electrode G and the body region 103 (hereinafter referred to as “contact area”) does not vary. However, as apparent from FIG. 22A, when the first contact C1 deviates toward a direction away from the center of the gate electrode G in the Y direction (hereinafter referred to as “+Y direction), the contact area A1 between the first contact C1 and the body region 103 increases, whereas the contact area A2 between the first contact C1 and the gate electrode G decreases. Accordingly, when the first contact C1 deviates toward the +Y direction, the contact resistance of the first contact C1 to the body region 103 decreases, while, to the contrary, the contact resistance of the first contact C1 to the gate electrode G increases. On the other hand, when the first contact C1 deviates toward a direction toward the center of the gate electrode G (hereinafter referred to as “−Y direction”), the contact area A1 between the first contact C1 and the body region 103 decreases, whereas the contact area A2 between the first contact C1 and the gate electrode G increases. Accordingly, when the first contact C1 deviates in the −Y direction, the contact resistance of the first contact C1 to the body region 103 increases, while, to the contrary, the contact resistance of the first contact C1 to the gate electrode G decreases. In this way, in the conventional structure the contact resistance varies with positional deviation of the first contact C1 in the Y direction.
However, the occurrence of such positional deviation and dimensional variation of the first contact C1 during substrate processing is an essential problem, which necessarily arises in the fabrication of semiconductor devices. This problem is unavoidable. Such positional deviation and dimensional variation occur due mainly to a lithography process for transferring a pattern to a semiconductor substrate. Since positional deviation and dimensional variation due to the lithography process depend upon the performance of a lithography apparatus used and the environment where the lithography apparatus is used, they constitute an unavoidable problem. In fabrication plants strict control is made over positional deviation and dimensional variation in the lithography process. Taking specific values for instance, with a lithography apparatus using i-line as a light source, control is made so as to suppress the amount of positional deviation to about ±0.15 μm and the amount of dimensional variation to about 20% of a minimum size; with a lithography apparatus using KrF as a light source, control is made so as to suppress the amount of positional deviation to about ±0.10 μm and the amount of dimensional variation to about 10% of a minimum size.